TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 271

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

10.14
10.14.1
10.14.1.1
10.14.1.2
Interrupt/Error Generation Timing
Figure 10-10 shows the data flow of receive operation and the route of read.
are given as follows.
SCxRFC<RFIS > setting are established.
RX Interrupts
Table 10-12 Receive Interrupt conditions in use of FIFO
RX interrupts are generated at the time depends on the transfer mode and the buffer configurations, which
In use of FIFO, receive interrupt is generated on the condition that the following either operation and
Interrupt conditions are decided by the SCxRFC<RFIS> settings as described in Table 10-12.
Configurations
Note:Interrupts are not generated when an overrun error is occurred.
Double Buffer
SCxRFC<RFIS>
Single Buffer
Single Buffer / Double Buffer
FIFO
Buffer
・ Reception completion of all bits of one frame.
・ Reading FIFO
Figure 10-10 Receive Buffer/FIFO Configuration Diagram
"0"
"1"
−
・Around the center of the first stop bit
"The fill level of FIFO" is equal to "the fill level of FIFO interruption generation."
"The fill level of FIFO" is greater than or equal to "the fill level of FIFO intrruption generation."
UART modes
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Interrupt conditions
・Immediately after the raising / falling edge of the last SCLK
(Rising or falling is determined according to SCxCR<SCLKS> setting.)
・Immediately after the raising / falling edge of the last SCLK
(Rising or falling is determined according to SCxCR<SCLKS> setting.)
・On data transfer from the shift register to the buffer by reading buffer.
IO interface modes
TMPM333FDFG/FYFG/FWFG