TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 17

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13. Watchdog Timer(WDT)
14. Real Time Clock (RTC)
13.1 Configuration.......................................................................................................................341
13.2 Register................................................................................................................................342
13.3 Operations............................................................................................................................344
13.4 Operation when malfunction (runaway) is detected............................................................345
13.5 Control register....................................................................................................................347
14.1 Function...............................................................................................................................349
14.2 Block Diagram.....................................................................................................................349
14.3 Detailed Description Register..............................................................................................350
14.4 Operational Description.......................................................................................................359
14.5 Alarm function.....................................................................................................................362
12.4.3
12.4.4
12.4.5
13.2.1
13.2.2
13.3.1
13.3.2
13.4.1
13.4.2
13.5.1
13.5.2
13.5.3
14.3.1
14.3.2
14.3.3
14.4.1
14.4.2
14.4.3
14.5.1
14.5.2
14.5.3
12.4.5.1
12.4.5.2
12.4.5.3
12.4.5.4
12.4.5.5
12.4.5.6
12.4.5.7
13.5.3.1
13.5.3.2
13.5.3.3
13.5.3.4
14.3.3.1
14.3.3.2
14.3.3.3
14.3.3.4
14.3.3.5
14.3.3.6
14.3.3.7
14.3.3.8
14.3.3.9
14.3.3.10
14.3.3.11
AD Monitor Function....................................................................................................................................................333
Selecting the Input Channel...........................................................................................................................................334
AD Conversion Details..................................................................................................................................................334
WDMOD(Watchdog Timer Mode Register) ................................................................................................................342
WDCR (Watchdog Timer Control Register).................................................................................................................343
Basic Operation..............................................................................................................................................................344
Operation Mode and Status............................................................................................................................................344
INTWDT interrupt generation.......................................................................................................................................345
Internal reset generation.................................................................................................................................................346
Watchdog Timer Mode Register (WDMOD)................................................................................................................347
Watchdog Timer Control Register(WDCR)..................................................................................................................347
Setting example..............................................................................................................................................................348
Register List...................................................................................................................................................................350
Control Register.............................................................................................................................................................350
Detailed Description of Control Register......................................................................................................................352
Reading clock data.........................................................................................................................................................359
Writing clock data..........................................................................................................................................................359
Entering the Low Power Consumption Mode...............................................................................................................361
1Hz cycle "Low" pulse1 Hz...........................................................................................................................................363
16Hz cycle "Low" pulse16 Hz.......................................................................................................................................363
"Low" pulse (when the alarm register corresponds with the clock).............................................................................362
Starting AD Conversion
AD Conversion
Top-priority AD conversion during normal AD conversion
Stopping Repeat Conversion Mode
Reactivating normal AD conversion
Conversion completion
Interrupt generation timings and AD conversion result storage register
Disabling control
Enabling control
Watchdog timer clearing control
Detection time of watchdog timer
RTCSECR (Second column register (for PAGE0 only))
RTCMINR (Minute column register (PAGE0/1))
RTCHOURR (Hour column register(PAGE0/1))
RTCDAYR (Day of the week column register(PAGE0/1))
RTCDATER (Day column register (for PAGE0/1 only))
RTCMONTHR (Month column register (for PAGE0 only))
RTCMONTHR (Selection of 24-hour clock or 12-hour clock24(for PAGE1 only))
RTCYEARR (Year column register (for PAGE0 only))
RTCYEARR (Leap year register (for PAGE1 only))
RTCPAGER(PAGE register(PAGE0/1))
RTCRESTR (Reset register (for PAGE0/1))
ix