TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 39

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

2.4
2.5
2.6
instruction execution. If an event is input, the core returns from low-power consumption mode caused by WFE in-
struction.
instruction and WFE instruction.
SLEEPDEEP signals are output when <SLEEPDEEP> bit of System Control Register is set.
is set.
also event signals are not used so that please do not use WFE instruction.
does not use this function.
Events
Power Management
Exclusive access
The Cortex-M3 core has event output signals and event input signals. An event output signal is output by SEV
TMPM333FDFG/FYFG/FWFG does not use event output signals and event input signals. Please do not use SEV
The Cortex-M3 core provides power management system which uses SLEEPING signals and SLEEPDEEP signals.
These signals are output in the following circumstances:
-Wait-For-Interrupt (WFI) instruction execution
-Wait-For-Event (WFE) instruction execution
-the timing when interrupt-service-routine (ISR) exit in case that <SLEEPONEXIT> bit of System Control Register
TMPM333FDFG/FYFG/FWFG does not use SLEEPDEEP signals so that <SLEEPDEEP> bit must not be set. And
For detail of power management, refer to the Chapter "Clock/Mode control."
In Cortex-M3 core, the DCode bus system supports exclusive access. However TMPM333FDFG/FYFG/FWFG
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TMPM333FDFG/FYFG/FWFG