TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 276
TMPM333FDFG
Manufacturer Part Number
TMPM333FDFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
Manufacturer
Toshiba
Specifications of TMPM333FDFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
512K
Rom Type
Flash
Ram (kbytes)
32K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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10.16
Operation in Each Mode
(2)
SCLK Input Mode
・ If double buffering is disabled (SCxMOD2<WBUF> = "0")
・ If double buffer is enabled (SCxMOD2<WBUF> = "1")
is outputted from the TXD pin. When all data is output, an interrupt INTTXx is generated. The
next transmit data must be written before the timing point "A" as shown in Figure 10-13.
data to the transmit buffer before the SCLK input becomes active or when data transmission
from the transmit shift register is completed. Simultaneously, the transmit buffer empty flag
SCxMOD2<TBEMP> is set to "1", and the INTTXx interrupt is generated.
bit counter is started, an under-run error occurs and 8-bit dummy data (0xFF) is sent.
If the SCLK is input in the condition where data is written in the transmit buffer, 8-bit data
Data is moved from the transmit buffer to the transmit shift register when the CPU writes
If the SCLK input becomes active while no data is in the transmit buffer, although the internal
Page 256
TMPM333FDFG/FYFG/FWFG
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