TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 90

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

7.5
Interrupts
7.5.2.3
active level specified in the clock generator, and is notified to the CPU.
request must be held at the active level until it is detected, otherwise the interrupt request will cease to exist
when the signal level changes from active to inactive.
to the CPU until the interrupt request is cleared in the CG Interrupt Request Clear (CGICRCG) Register. If
a standby mode is exited without clearing the interrupt request, the same interrupt will be detected again when
normal operation is resumed. Be sure to clear each interrupt request in the ISR.
(7)
If an interrupt source is used for exiting a standby mode, an interrupt request is detected according to the
An edge-triggered interrupt request, once detected, is held in the clock generator. A level-sensitive interrupt
When the clock generator detects an interrupt request, it keeps sending the interrupt signal in "High" level
Detection by Clock Generator
unexpected interrupt.To clear corresponding interrupt request, write a value corresponding to the in-
terrupt to be used to the CGICRCG register.See "7.6.3.4 CGICRCG(CG Interrupt Request Clear
Register)" for each value.
used for exiting a standby mode. However, an "High" pulse or "High"-level signal must be input so that
the CPU can detect it as an interrupt request. Also, be aware of the description of"7.5.1.4 Precautions
when using external interrupt pins".
with the Interrupt Set-Enable Register. Each bit of the register is assigned to a single interrupt source.
interrupt. Writing "1" to the corresponding bit of the Interrupt Set-Enable Register enables the intended
interrupt.
lost if pending interrupts are cleared. Thus, this operation is not necessary.
Note 1: m : corresponding bit
Note 2: PRIMASK register cannot be modified by the user access level.
Clock generator register
CGIMCGn<EMCGm>
CGICRCG<ICRCG>
CGIMCGn<INTmEN>
NVIC register
Interrupt Clear-Pending [m]
Interrupt Set-Enable [m]
Interrupt mask register
PRIMASK
Before enabling an interrupt, clear the corresponding interrupt request already held. This can avoid
Interrupt requests from external pins can be used without setting the clock generator if they are not
Enable the interrupt by the CPU as shown below.
Clear the suspended interrupt in the Interrupt Clear-Pending Register. Enable the intended interrupt
Writing "1" to the corresponding bit of the Interrupt Clear-Pending Register clears the suspended
To generate interrupts in the Interrupt Set-Pending Register setting, factors to trigger interrupts are
At the end, PRIMASK register is zero cleared.
Note:n: register number / m: number assigned to interrupt source
Enabling interrupt by CPU
←
←
←
active level
Value corresponding to the interrupt to be used
"1" (interrupt enabled)
←
←
←
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"1"
"1"
"0"
TMPM333FDFG/FYFG/FWFG