TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 357

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

(2)
(3)
TADHP) is generated, and ADMOD2<EOCFHP> which indicates the completion of top-priority AD
conversion is set to "1".
AD conversion is completed, ADMOD0<EOCFN> is set to "1". To confirm the completion of AD
conversion and to obtain the results, poll this bit.
and <ADRxRF> = “1”, a correct conversion result has been obtained.
After the AD conversion is completed, the top-priority AD conversion completion interrupt (IN-
AD conversion results are stored in the AD conversion result register SP.
To confirm the completion of AD conversion without using interrupts, data polling can be used. When
AD conversion result storage register must be read by half word or word access. If <OVRx> = “0”
Top-priority AD conversion completion
Data polling
・ Channel scan repeat conversion mode
request INTAD is generated. ADMOD0<ADBFN> is not cleared to "0". It remains at "1".
channel.
c. 8 conversions
Each time one AD conversion is completed, ADMOD0<EOCF> is set to "1" and interrupt
AD conversion results are stored in a AD conversion result register corresponding to a
With <ITM[1:0]> set to "10", an interrupt request is generated each time eight AD con-
versions are completed. In this case, the conversion results are sequentially stored in the
storage register ADREG08 through ADREG7F. After the conversion result is stored in
ADREG7F, <EOCFN> is set to "1", and the storage of subsequent conversion results
starts from ADREG08.
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TMPM333FDFG/FYFG/FWFG