TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 302

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.5
Control in the I2C Bus Mode
11.5.6
11.5.7
11.5.8
SCLx pin
SDAx pin
as a receiver.
set to "0".
transmitted, <TRX> is set to "0" by the hardware. If the direction bit is "0", <TRX> changes to "1". If the SBI
does not receive acknowledgement, <TRX> retains the previous value.
detects the stop condition on the bus or the arbitration lost.
for generating the start condition and to output the slave address and the direction bit prospectively written in the
data buffer register. <ACK> must be set to "1" in advance.
generating the stop condition on the bus. The contents of <MST, TRX, BB, PIN> should not be altered until the
stop condition appears on the bus.
generated after the SCL line is released.
Setting SBIxCR2<TRX> to "1" configures the SBI as a transmitter. Setting <TRX> to "0" configures the SBI
At the slave mode:
If the value of the direction bit (R/W) is "1", <TRX> is set to "1" by the hardware. If the bit is "0", <TRX> is
As a master device, the SBI receives acknowledgement from a slave device. If the direction bit of "1" is
<TRX> is cleared to "0" by the hardware when it detects the stop condition on the bus or the arbitration lost.
If SBI is used in free data format, <TRX> is not changed by the hardware.
Setting SBIxCR2<MST> to "1" configures the SBI to operate as a master device.
Setting <MST> to "0" configures the SBI as a slave device. <MST> is cleared to "0" by the hardware when it
When SBIxSR<BB> is "0", writing "1" to SBIxCR2<MST, TRX, BB, PIN> causes the SBI to start a sequence
When <BB> is "1", writing "1" to <MST, TRX, PIN> and "0" to <BB> causes the SBI to start a sequence for
If SCL bus line is pulled "Low" by other devices when the stop condition is generated, the stop condition is
Configuring the SBI as a Transmitter or a Receiver
Configuring the SBI as a Master or a Slave
Generating Start and Stop Conditions
・ when data is transmitted in the addressing format.
・ when the received slave address matches the value specified at SBIxI2CAR.
・ when a general-call address is received; i.e., the eight bits following the start condition are all zeros.
Start condition
Figure 11-5 Generating the Start Condition and a Slave Address
A6
1
A5
2
A4
Slave address and direction bit
3
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A3
4
A2
5
A1
6
A0
7
TMPM333FDFG/FYFG/FWFG
R/W
8
Acknowledgement signal
9