TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 16

• Manufacturer Part Number: TMPM333FDFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
• Manufacturer: Toshiba

Specifications of TMPM333FDFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 512K
• Rom Type: Flash
• Ram (kbytes): 32K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: -
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12. Analog/Digital Converter (ADC)
viii
11.6 Data Transfer Procedure in the I2C Bus ModeI2C.............................................................286
11.7 Control register of SIO mode..............................................................................................295
11.8 Control in SIO mode............................................................................................................301
12.1 Outline.................................................................................................................................309
12.2 Configuration.......................................................................................................................310
12.3 Registers..............................................................................................................................311
12.4 Description of Operations....................................................................................................332
11.5.10
11.5.11
11.5.12
11.5.13
11.5.14
11.5.15
11.5.16
11.6.1
11.6.2
11.6.3
11.6.4
11.6.5
11.7.1
11.7.2
11.7.3
11.7.4
11.7.5
11.7.6
11.8.1
11.8.2
12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
12.3.6
12.3.7
12.3.8
12.3.9
12.3.10
12.3.11
12.3.12
12.3.13
12.3.14
12.3.15
12.3.16
12.3.17
12.3.18
12.3.19
12.3.20
12.4.1
12.4.2
11.6.2.1
11.6.2.2
11.6.3.1
11.6.3.2
11.8.1.1
11.8.1.2
11.8.2.1
11.8.2.2
11.8.2.3
11.8.2.4
12.4.2.1
12.4.2.2
Device Initialization.......................................................................................................................................................286
Generating the Start Condition and a Slave Address.....................................................................................................286
Transferring a Data Word..............................................................................................................................................288
Generating the Stop Condition......................................................................................................................................293
Restart Procedure...........................................................................................................................................................293
SBIxCR0(control register 0)..........................................................................................................................................295
SBIxCR1(Control register 1).........................................................................................................................................296
SBIxDBR (Data buffer register)....................................................................................................................................297
SBIxCR2(Control register 2).........................................................................................................................................298
SBIxSR (Status Register)...............................................................................................................................................299
SBIxBR0 (Baud rate register 0).....................................................................................................................................300
Serial Clock....................................................................................................................................................................301
Transfer Modes..............................................................................................................................................................303
Register list....................................................................................................................................................................311
ADCBAS (Conversion Accuracy Setting Register)......................................................................................................312
ADCLK (Conversion Clock Setting Register)..............................................................................................................313
ADMOD0 (Mode Control Register 0) ..........................................................................................................................314
ADMOD1 (Mode Control Register 1)...........................................................................................................................315
ADMOD2 (Mode Control Register 2) ..........................................................................................................................317
ADMOD4 (Mode Control Register 4) ..........................................................................................................................319
ADMOD3 (Mode Control Register 3)...........................................................................................................................320
ADMOD5 (Mode Control Register 5)...........................................................................................................................321
Analog Reference Voltage.............................................................................................................................................332
AD Conversion Mode....................................................................................................................................................332
Arbitration Lost Detection Monitor.............................................................................................................................283
Slave Address Match Detection Monitor.....................................................................................................................285
General-call Detection Monitor...................................................................................................................................285
Last Received Bit Monitor...........................................................................................................................................285
Data Buffer Register (SBIxDBR)................................................................................................................................285
Baud Rate Register (SBIxBR0)...................................................................................................................................285
Software Reset.............................................................................................................................................................285
ADREG08 (Conversion Result Register 08)...............................................................................................................322
ADREG19 (AD Conversion Result Register 19)........................................................................................................323
ADREG2A (AD Conversion Result Register 2A)......................................................................................................324
ADREG3B (AD Conversion Result Register 3B).......................................................................................................325
ADREG4C (AD Conversion Result Register 4C).......................................................................................................326
ADREG5D (AD Conversion Result Register 5D)......................................................................................................327
ADREG6E (AD Conversion Result Register 6E).......................................................................................................328
ADREG7F (AD Conversion Result Register 7F)........................................................................................................329
ADREGSP (AD Conversion Result Register SP).......................................................................................................330
ADCMP0 (AD Conversion Result Comparison Register 0).......................................................................................331
ADCMP1 (AD Conversion Result Comparison Register 1).......................................................................................331
Master mode
Slave mode
Master mode (<MST> = "1")
Slave mode (<MST> = "0")
Clock source
Shift Edge
8-bit transmit mode
8-bit receive mode
8-bit transmit/receive mode
Data retention time of the last bit at the end of transmission
Normal AD conversion
Top-priority AD conversion