TMPM333FDFG Toshiba, TMPM333FDFG Datasheet - Page 257

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TMPM333FDFG

Manufacturer Part Number
TMPM333FDFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 512K FLASH, 32K SRAM
Manufacturer
Toshiba
Datasheets

Specifications of TMPM333FDFG

Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
512K
Rom Type
Flash
Ram (kbytes)
32K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
-
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM333FDFG
Manufacturer:
Toshiba
Quantity:
10 000
(2)
Table 10-8 Example of UART Mode Baud Rate (Using the Baud Rate Generator)
9.830400
by 16 in the receive counter or the transmit counter before use.
fc [MHz]
Table 10-7 shows the clock selection in the UART mode. In the UART mode, selected clock is divided
The examples of baud rate in each clock settings.
Transfer clock in the UART mode
・ If the baud rate generator is used
・ If the SCLK input is used
・ If fsys is used
following clock settings.
Table 10-7 Clock Selection in UART Mode
-
-
-
-
・ fc = 9.8304MHz
・ fgear = 9.8304MHz (CGSYSCR<GEAR[2:0]> = "000" : fc selected)
・ ΦT0 = 4.9152MHz (CGSYSCR<PRCK[2:0]> = "001" : 2 division ratio)
The highest baud rate is less than 40 ÷ 8 = 5.0 Mbps.
The highest baud rate is 1.25Mbps because 20MHz is divided by 16.
Table 10-8 shows examples of baud rate when the baud rate generator is used with the
To use SCLK input, the following conditions must be satisfied.
- SCLK cycle > 2/fsys
The highest baud rate must be less than 40 ÷ 2 ÷ 16 = 1.25 Mbps.
Since the highest value of fsys is 40MHz, the highest baud rate is 40 ÷ 16 = 2.5Mbps.
(SCxBRCR<BRS>)
fc = 40MHz
fgear = 40MHz (CGSYSCR<GEAR[2:0]> = "000" : fc selected)
ΦT0 = 40MHz (CGSYSCR<PRCK[2:0]> = "000" : 1 division ratio)
Clock = ΦT1 = 20MHz (SCxBRCR<BRCK[1:0]> = "00" : ΦT1 selected)
Division ratio N
SCxMOD0<SM>
UART Mode
16
Mode
2
4
8
Page 237
76.800
38.400
19.200
9.600
(fc/4)
φT1
Baud rate generator
SCxMOD0<SC>
Clock selection
Timer output
SCLK input
19.200
(fc/16)
9.600
4.800
2.400
φT4
fsys
(fc/64)
φT16
4.800
2.400
1.200
0.600
TMPM333FDFG/FYFG/FWFG
(fc/256)
Unit:kbps
φT64
1.200
0.600
0.300
0.150

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