Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 97

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

82
UM005003-0703
Interrupt Source
INT1
INT2
PRT channel 0
PRT channel 1
DMA channel 0
DMA channel 1
CSI/O
ASCI channel 0
ASCI channel 1
Z8018x
Family MPU User Manual
Interrupt Acknowledge Cycle Timings
individual I/O (PRT, DMAC, CSI/O, ASCI) control register. The lower
vector of INT1 INT2 and internal interrupt are summarized in Table 9.
Table 9.
Figure 43 illustrates INT1, INT2, and internal interrupts timing. INT1 and
INT2 are sampled at the falling edge of the clock state prior to T2 or T1 in
the last machine cycle. If INT1 or INT2 is asserted Low at the falling
edge of clock state prior to T3 or T1 in the last machine cycle, the
interrupt request is accepted.
Priority
Highest
Lowest
Vector Table
—
—
—
—
—
—
IL
b7
—
—
—
b6
—
—
—
—
—
—
—
—
—
b5
—
—
—
—
—
—
—
—
—
Fixed Code
b4
0
0
0
0
0
0
0
0
1
b3
0
0
0
0
1
1
1
1
0
b2
0
0
1
1
0
0
1
1
0
b1
0
1
0
1
0
1
0
1
0
b0
0
0
0
0
0
0
0
0
0