Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 173

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

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UM005003-0703
Z8018x
Family MPU User Manual
return accurate data without requiring the timer to be stopped. The write
procedure requires the PRT to be stopped.
For reading (without stopping the timer), TMDR is read in the order of
lower byte - higher byte (TMDRnL, TMDRnH). The lower byte read
(TMDRnL) stores the higher byte value in an internal register. The
following higher byte read (TMDRnH) accesses this internal register.
This procedure insures timer data validity by eliminating the problem of
potential 16-bit timer updating between each 8-bit read. Specifically,
reading TMDR in higher byte–lower byte order may result in invalid data.
Note the implications of TMDR higher byte internal storage for
applications which may read only the lower and/or higher bytes. In
normal operation all TMDR read routines must access both the lower and
higher bytes, in that order. For writing, the TMDR down counting must be
inhibited using the TDE (Timer Down Count Enable) bits in the TCR
(Timer Control Register). Then, any or both higher and lower bytes of
TMDR can be freely written (and read) in any order.
CSI/O Transmit/Receive Data Register (TRDR: I/O
Address = 0BH).
TRDR is used for both CSI/O transmission and reception. Thus, the
system design must insure that the constraints of half-duplex operation
are met (Transmit and receive operation cannot occur simultaneously).
For example, if a CSI/O transmission is attempted while the CSI/O is
receiving data, the CSI/O does not work.
TRDR is not buffered. Attempting to perform a CSI/O transmit while the
previous transmit data is still being shifted out causes the shift data to be
immediately updated, thereby corrupting the transmit operation in
progress. Similarly, reading TRDR during a transmit or receive must be
avoided.