Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 45

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

30
Table 4.
UM005003-0703
Note:
1.
2.
IWI1 IWI0
Z8018x
Family MPU User Manual
0
0
1
1
For Z8X180 internal I/O register access (I/O addresses
determine wait state (TW) timing. For ASCI, CSI/O and PRT Data Register accesses, 0 to 4 Wait States
(TW) are generated. The number of Wait States inserted during access to these registers is a function of
internal synchronization requirements and CPU state. All other on-chip I/O register accesses (that is,
MMU, DMAC, ASCI Control Registers, for instance.) have no Wait States inserted and thus require only
three clock cycles.
For interrupt acknowledge cycles in which M1 is High, such as interrupt vector table read and PC
stacking cycle, memory access timing applies.
0
1
0
1
Wait State Insertion
For external
accesses
I/O registers
inserted depending on the programmed value in IWI1 and IWI0. Refer to
Table 4.
WAIT Input and RESET
During RESET, MWI1, MWI0 IWI1 and IWI0, are all
maximum number of Wait States (TW) (three for memory accesses, four
for external I/O accesses).
1
2
3
4
For internal
I/0
registers
accesses
(Note 1)
0
The Number of Wait States
For INT0
interrupt
acknowledge
cycles when
M1 is Low
0000H
2
4
5
6
-
003FH
For INT1,
INT2 and
internal
interrupts
acknowledge
cycles
(Note 2)
), IWI1 and IWI0 do not
2
1
, selecting the
For NMI
interrupt
acknowledge
cycles
when M1 is
Low
(Note 2)
0