Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 148

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

Bit
Position Bit/Field R/W
5
4
3
2
–
0
CTS/PS
PEO
DR
SS2
–
0
The external ASCI channel 0 data clock pins are multiplexed with DMA
control lines (CKA0/DREQ and CKA1/TEND0). During RESET, these
R/W
R/W
R/W
R/W
Value
Description
Clear to Send/Prescale — When read,
the state of the external
is High,
High, the TDRE bit is inhibited (that is, held at 0). For
channel 1, the
(Clocked Serial Receive Data). Thus,
valid when read if the channel 1 CTS1E bit is 1 and the
CST1 input pin function is selected. The read data of
CTS
When written, CT /PS specifies the baud rate generator
prescale factor. If
prescaled by 30 while if
system clock is prescaled by 10.CTS/PS is cleared to 0
during RESET.
Parity Even Odd — PE0 selects even or odd parity. PE0
does not affect the enabling/disabling of parity (MOD1
bit of CNTLA). If PE0 is cleared to 0, even parity is
selected. If PE0 is set to 1, odd parity is selected.PE0 is
cleared to 0 during RESET.
Divide Ratio — DR specifies the divider used to obtain
baud rate from the data sampling clock If DR is reset to 0,
divide by 16 is used, while if DR is set to 1, divide by 64
is used. DR is cleared to 0 during RESET.
Source/Speed Select — Specifies the data clock source
(internal or external) and baud rate prescale factor. SS2,
SS1, and SS0 are all set to 1 during RESET. Table 18
describes the divide ratio corresponding to SS2, SS1 and
SS0
/PS is not affected by RESET.
CTS
/PS is read as 1. When the
CTS
CTS
1 input is multiplexed with RXS pin
/PS is set to 1, the system clock is
Family MPU User Manual
CTS
CTS
input. If the
/PS is cleared to 0, the
CTS
UM005003-0703
CTS
CTS
CTS
/PS is only
/PS reflects
Z8018x
input pin is
input pin
133