Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 130
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Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
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Z8018x
Family MPU User Manual
115
If the falling edge of NMI occurs before the falling clock of the state prior
to T3 (T2 or Tw) of the DMA write cycle, the DMAC is suspended and
the CPU starts the NMI response at the end of the current cycle. By
setting a channel's DE bit to
, the channel's operation is restarted and
1
DMA correctly resumes from its suspended point by NMI. (Reference
Figure 51.)
DMA read cycle
DMA write cycle
NMI acknowledge cycle
T1
T2
T3
T1
T2
T3
T1
Phi
NMI
DME = “0” (DMA Stop)
Figure 51.
NMI and DMA Operation Timing Diagram
DMAC and RESET
During RESET the bits in DSTAT, DMODE, and DCNTL are initialized
as stated in their individual register descriptions. Any DMA operation in
progress is stopped, allowing the CPU to use the bus to perform the
RESET sequence. However, the address register (SAR0, DAR0 MAR1,
IAR1) and byte count register (BCR0 BCR1) contents are not changed
during RESET.
Asynchronous Serial Communication Interface (ASCI)
The Z8X180 on-chip ASCI has two independent full-duplex channels.
Based on full programmability of the following functions, the ASCI
directly communicates with a wide variety of standard UARTs (Universal
Asynchronous Receiver/Transmitter) including the Z8440 SIO and the
Z85C30 SCC.
UM005003-0703
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