Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 314

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

298
UM005003-0703
Register
Timer Data Register
Channel 1L:
Timer Data Register
Channel 1H:
Timer Reload Register
Channel 1L
Timer Reload Register
Channel 1H:
Free Running Counter:
DMA Source Address
Register Channel 0L:
DMA Source Address
Register Channel 0H:
DMA Source Address
Register Channel 0B:
DMA Destination Address
Register Channel 0L:
DMA Destination Address
Register Channel 0H:
DMA Destination Address
Register Channel 0B:
DMA Byte Count Register
Channel 0L:
DMA Byte Count Register
Channel 0H:
DMA Memory Address
Register
Channel 1L:
DMA Memory Address
Register
Channel 1H:
Z8018x
Family MPU User Manual
Table 57.
TMDR1L
TMDR1H
RLDR1L
RLDR1H
FRC
SAR0L
SAR0H
SAR0B
DAR0L
DAR0H
DAR0B
BCROL
BCROH
MAR1L
MAR1H
Mnemonics Address
Internal I/O Registers (Continued)
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
6
9
4
5
7
8
0
1
2
3
4
5
6
7
8
Read only
* In the R1 and Z mask, these DMAC registers are expanded from 4 bits to 3 bits in the
package version of CP-68.
Bits 0-2 (3) are used for SAR0B
Bits 0-2 (3) are used for DAR0B
A
A
X
X
X
X
19
X
X
X
X
19
*,
*,
A
A
X
X
X
X
X
X
X
X
18
18
,
,
A
A
0
0
1
1
17
0
0
1
1
17
,
,
A
A
0
1
0
1
0
1
0
1
16
16
Remarks
DMA Transfer Request
DMA Transfer Request
RDR0 (ASCI0)
Not used
DREQ
RDR1 (ASCI1)
DREQ
TDR0 (ASCI0)
Not used
TDR1 (ASCI1)
0
0
(external)
(external)