Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 8
![IC 10MHZ Z180 CMOS ENH MPU 64DIP](/photos/6/76/67665/z8018010psg_sml.jpg)
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
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- Download datasheet (5Mb)
List of Figures
Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10. Op Code Fetch (with Wait State) Timing Diagram . . . . . .20
Figure 11. Memory Read/Write (without Wait State)
Figure 12. Memory Read/Write (with Wait State)
Figure 13. I/O Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . .23
Figure 14. Instruction Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 15. RESET Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 16. Bus Exchange Timing During Memory Read . . . . . . . . . . .26
Figure 17. Bus Exchange Timing During CPU Internal Operation . . .27
Figure 18. WAIT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 19. Memory and I/O Wait State Insertion
Figure 20. HALT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .33
64-Pin DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
80-Pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Z80180/Z8S180/Z8L180 Block Diagram . . . . . . . . . . . . . . .6
Operation Mode Control Register . . . . . . . . . . . . . . . . . . . .15
M1 Temporary Enable Timing . . . . . . . . . . . . . . . . . . . . . .16
I/O Read and Write Cycles with IOC = 1
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
I/O Read and Write cycles with IOC = 0
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Op Code Fetch (without Wait State) Timing Diagram . . . .19
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
(DCNTL – DMA/Wait Control Register) . . . . . . . . . . . . . .29
Family MPU User Manual
UM005003-0703
Z8018x
ix
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