Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 11

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

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Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Z8018x
Family MPU User Manual
Figure 74. CPU Register Configurations . . . . . . . . . . . . . . . . . . . . . 176
Figure 75. Register Direct — Bit Field Definitions . . . . . . . . . . . . . 181
Figure 76. Register Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . 181
Figure 77. Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 78. Extended Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 79. Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 80. Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 81. AC Timing Diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 82. AC Timing Diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 83. CPU Timing (IOC = 0) (I/O Read Cycle,
Figure 84. DMA Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 85. E Clock Timing (Memory R/W Cycle) (I/O R/W Cycle) 201
Figure 86. E Clock Timing (BUS RELEASE Mode, SLEEP Mode, and
Figure 87. E Clock Timing (Minimum Timing Example of PWEL and
Figure 88. Timer Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 89. SLP Execution Cycle Timing Diagram . . . . . . . . . . . . . . 203
Figure 90. CSI/O Receive/Transmit Timing Diagram . . . . . . . . . . . 204
Figure 91. External Clock Rise Time and Fall Time . . . . . . . . . . . . 204
Figure 92.
Figure 93. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
I/O Write Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
SYSTEM STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 201
PWEH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
(Except EXTAL, RESET) . . . . . . . . . . . . . . . . . . . . . . . . 204
Input Rise Time and Fall Time
UM005003-0703