Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 35
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
Z8018010PSG
Manufacturer:
Zilog
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UM005003-0703
Z8018x
Family MPU User Manual
Figure 10.
Operand and Data Read/Write Timing
The instruction operand and data read/write timing differs from Op Code
fetch timing in two ways:
•
•
Instruction operands include immediate data, displacement, and extended
addresses, and contain the same timing as memory data reads.
During memory write cycles the MREQ signal goes active in the second
half of T1. At the end of T1, the data bus is driven with the write data.
At the start of T2, the WR signal is asserted Low enabling the memory.
MREQ and WR go inactive in the second half of T3 followed by
disabling of the write data on the data bus.
A0
D0
MREQ
WAIT
–
The M1 output is held inactive
The read cycle timing is relaxed by one-half clock cycle because data
is latched at the falling edge of T3
–
A19
Phi
RD
M1
D7
Op Code Fetch (with Wait State) Timing Diagram
T1
T2
TW
TW
Op Code
T3
T1
T2
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