Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 297

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

Operating Modes Summary
REQUEST ACCEPTANCES IN EACH OPERATING MODE
Request
WAIT
Refresh Request
Request of Refresh
by the on-chip
Refresh Controller
DREQ0
DREQ1
BUSREQ
Interrupt INT0,
INT1,
1NT2
Current
Status
Normal
Operation
(CPU mode
and IOSTOP
Mode)
Acceptable
Refresh cycle
begins at the
end of Machine
Cycle (MC)
DMA cycle
begins at the
end of MC
Bus is released
at the end of
MC
Accepted after
executing the
current
instruction.
Table 53.
WAIT State
Acceptable
Not
acceptable
DMA cycle
begins at the
end of MC
Not
acceptable
Accepted
after
executing the
current
instruction
Request Acceptances in Each Operating Mode
Refresh
Cycle
Not
acceptable
Not
acceptable
Acceptable
Refresh cycle
precedes.
DMA cycle
begins at the
end of one
MC
Not
acceptable
Not
acceptable
Interrupt
Acknowledge
Cycle
Acceptable
Refresh cycle
begins at the
end MC
Acceptable
DMA cycle
begins at the
end of MC.
Bus is released
at the end of
MC
Not
acceptable
DMA Cycle
Acceptable
Refresh cycle
begins at the
end of MC
Acceptable
Refer to
“DMA
Controller”
for details.
Bus is
released at the
end of MC
Not
acceptable
Family MPU User Manual
BUS
RELEASE
Mode
Not
acceptable
Not
acceptable
Acceptable
*After BUS
RELEASE
cycle, DMA
cycle begins
at the end of
one MC
Continue
BUS
RELEASE
mode
Not
acceptable
UM005003-0703
SLEEP
Mode
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable
Acceptable
Return from
SLEEP
mode to
normal
operation.
Z8018x
SYSTEM
STOP
Mode
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable
Acceptable
Return from
SYSTEM
STOP mode
to normal
operation
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