Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 125

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

110
UM005003-0703
Z8018x
Family MPU User Manual
DREQ0 for ASCI transmission and reception respectively. To initiate
memory to/from ASCI DMA transfer, perform the following operations:
1. Load the source and destination addresses into SAR0 and DAR0
Table 16.
Note: X = Don’t care
Note: X = Don’t care
DAR18
SAR18
Specify the I/O (ASCI) address as follows:
a. Bits A0–A7 must contain the address of the ASCI channel
b. Bits A8–A15 must equal 0.
c. Bits SAR17–SAR16 must be set according to Table 16 to enable
X
X
X
X
X
X
X
X
transmitter or receiver (I/O addresses
use of the appropriate ASCI status bit as an internal DMA
request.
DAR17
DMA Transfer Request
SAR17
0
0
1
1
0
0
1
1
DAR16 DMA Transfer Request
SAR16 DMA Transfer Request
0
1
0
1
0
1
0
1
DREQ0
RDRF (ASCI channel 0)
RDRF (ASCI channel 1)
Reserved
DREQ0
TDRE (ASCI channel O)
TDRE (ASCI channel 1)
Reserved
6H
-
9H
).