Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 121

IC 10MHZ Z180 CMOS ENH MPU 64DIP

Z8018010PSG

Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Datasheets

Specifications of Z8018010PSG

Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
106
UM005003-0703
Z8018x
Family MPU User Manual
Figure 46.
To initiate memory to/from memory DMA transfer for channel 0, perform
the following operations.
1. Load the memory source and destination address into SAR0 and DAR0
2. Specify memory to/from memory mode and address increment/
3. Load the number of bytes to transfer in BCR0.
4. Specify burst or cycle steal mode in the MMOD bit of DCNTL.
5. Program DE0 =
decrement in the SM0 SM1, DM0 and DM1 bits of DMODE.
the DMA operation starts one machine cycle later. If interrupt occurs
at the same time, the DIE0 bit must be set to
Address
MREQ
Data
WR
Phi
RD
DMA Timing Diagram-CYCLE STEAL Mode
DMA cycle
1
T1
(with DWE0 =
CPU cycle
LD g,m
Op Code
address
T2
m
T3
T1
DMA cycle (transfer 1 byte)
Source
memory
address
T2
Read data
0
T3
in the same access) in DSTAT and
T1
Destination
memory
address
T2
Write data,
T3
1
T1
.
CPU cycle
LD g,m
operand
address
T2
T3
m
T1
DMA cycle
T2

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