Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 160
![IC 10MHZ Z180 CMOS ENH MPU 64DIP](/photos/6/76/67665/z8018010psg_sml.jpg)
Z8018010PSG
Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Specifications of Z8018010PSG
Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG
Z8018010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
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2^ss depends on the three least significant bits of the CNTLB register, as
described in Table 21.
Table 21. 2^ss Values
The ASCIs require a 50% duty cycle when CKA is used as an input.
Minimum High and Low times on CKA0 are typical of most CMOS
devices.
RDRF is set, and if enabled, an Rx Interrupt or DMA REquest is
generated when the receiver transfers a character from the Rx Shift
Register to the RX FIFO. The FIFO provides a margin against overruns.
When the is more than one character in the FIFO, and software or a DMA
channel reads a character, RDRF either remains set or is cleared and then
immediately set again. For example, if a receive interrupt service routine
does not real all the characters in the RxFIFO, RDRF and the interrupt
request remain asserted.
The Rx DMA request is disabled when any of the error flags PE or FE or
OVRN are set, so that software can identify with which character the
problem is associated.
If Bit 7, RDRF Interrupt Inhibit, is set to 1, the ASCI does not request a
Receive interrupt when its RDRF flag is 1. Set this bit when programming
a DMA channel to handle the receive data from an ASCI. The other
ss2
0
0
0
0
1
1
1
1
ss1
0
0
1
1
0
0
1
1
ss0
0
1
0
1
0
1
0
1
2^ss
1
2
4
8
16
32
64
External Clock from CKA0
Family MPU User Manual
UM005003-0703
Z8018x
145
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