Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 127

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

112
UM005003-0703
Z8018x
Family MPU User Manual
Note:
Note:
4. Specify whether DREQ1 is level- or edge- sense in the DMS1 bit in
5. Enable or disable DMA termination interrupt with the DIE1 bit in
6. Program DE1 =
DMA Bus Timing
When memory (and memory mapped I/O) is specified as a source or
destination, MREQ goes Low during the memory access. When I/O is
specified as a source or destination, IORQ goes Low during the I/O access.
When I/O (and memory mapped I/O) is specified as a source or
destination, the DMA timing is controlled by the external DREQ input
and the TEND output indicates DMA termination
For I/O accesses, one Wait State is automatically inserted. Additional
Wait States can be inserted by programming the on-chip wait state
generator or using the external WAIT input.
For memory to memory transfers (channel 0 only), the external DREQ0
input is ignored. Automatic DMA timing is programmed as either
BURST or CYCLE STEAL.
When a DMA memory address carry/borrow between bits A15 and A16
of the address bus occurs (crossing 64KB boundaries), the minimum bus
DCNTL.
DSTAT.
and the DMA operation with the external I/O device begins using the
external DREQ1 input and TEND1 output.
External I/O devices may not overlap addresses with internal I/O
and control registers, even using DMA.
For memory mapped I/O accesses, this automatic I/O Wait State
is not inserted.
1
(with DWE1 = 0 in the same access) in DSTAT