Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 242

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

226
Table 43.
UM005003-0703
Operation
Name
(2) P/V = 0: BC
(3) Z = 1: Ar = (HL)
Z8018x
Family MPU User Manual
P/V = 1: BC
Z = 0 :Ar ¹ (HL)
Mnemonics Op Code
CPI
CPIR
LDD
LDDR
LDI
LDIR
R
Block Transfer (Continued)
-1 = 0
M
R
-1 ¹ 0
11101101
10100001
11101101
10110001
11 101 101
10 101 000
11 101 101
10 111 000
11 101 101
10 100 000
11 101 101
10 110 000
M
Immed Ext Ind Reg RegI Imp Rel
Addressing
S
S
S/D
S/D
S/D
S/D
S
S
Bytes States
2
2
2
2
2
2
12
14
12
12
14(BC
12(BC
12
14(BC
12(BC
R
R
R
R
¹0)
¹ 0)
= 0)
= 0)
Operation
Ar-(HL)
BC
HL
BC
BC
Q
Repeat Q until
Ar = (HL)
(HL)
BC
DE
HL
Q
Repeat Q until
BC
(HL)
BC
DE
HL
Q
Repeat Q until
BC
R
R
R
R
R
R
R
R
R
R
R
R
-1®HL
M
M
-1®BC
-1®DE
-1®BC
+ 1®HL
+ 1®HL
= 0 or Ar = (HL)
-1®BC
= 0
+ 1®DE
= 0
¹ 0 Ar*(HL)
®DE)
® (DE)
M
(HL)
BC
DE
HL
(HL)
DE
BC
HL
M
Ar-(HL)
BC
HL
or BC
R
R
R
R
R
R
R
R
R
R
R
M
R
R
R
M
R
-1 ® HL
R
-1 ® BC
-1 ® DE
-1®BC
R
M
+ 1®DE
+ 1®HL
-1®BC
® (DE)
®(DE)
+ 1®HL
M
M
R
= 0
M
R
M
R
R
M
R
R
R
R
R
7 6
S Z
­ ­
­ ­
· ·
· ·
· ·
· ·
(3)
4 2
H P/V N C
­ ­
­ ­
R ­
R R
R ­
R R
Flags
(2)
(2)
(2)
1 0
S ·
S ·
R ·
R ·
R ·
R ·