Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 30

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

OPERATION MODES
Operation Mode Control Register
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate? = Not Applicable
M1E
R/W
7
1
The Z8X180 can be configured to operate like the Hitachi HD64180. This
functionality is accomplished by allowing user control over the M1,
IORQ, WR, and RD signals. The Operation Mode Control Register
(OMCR), illustrated in Figure 5, determines the M1 options, the timing of
the IORQ, RD, and WR signals, and the RETI operation.
Figure 5.
M1E (M1 Enable): This bit controls the M1 output and is set to a
RESET.
When M1E is
cycle, the INT0 acknowledge cycle, and the first machine cycle of the
NMI acknowledge. This action also causes the M1 signal to be Active
during both fetches of the RETI instruction sequence, and may cause
corruption of the external interrupt daisy chain. Therefore, this bit must be
0
asserted Low only during the refetch of the RETI instruction sequence
and the INT0 acknowledge cycle (Figure 6).
for the Z8X180. When M1E is
M1TE
W
6
1
Operation Mode Control Register
1
, the M1 output is asserted Low during the Op Code fetch
R/W
IOC
5
1
4
0
the M1 output is normally inactive and
Family MPU User Manual
Reserved
–
–
UM005003-0703
Z8018x
1
during
0
15