Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 181

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

166
UM005003-0703
Z8018x
Family MPU User Manual
These devices require connection with the Z8X180 synchronous E clock
output. The speed (access time) required for the peripheral devices are
determined by the Z8X180 clock rate. Table 24, and Figure 67 through
Figure 70 define E clock output timing.
Wait States are inserted in Op Code fetch, memory read/write, and I/O
read/write cycles which extend the duration of E clock output High.
During I/O read/write cycles with no Wait States (only occurs during on-
chip I/O register accesses), E does not go High.
Table 24.
Condition
Op Code Fetch Cycle
Memory Read/Write Cycle
I/O read Cycle
I/O Write Cycle
NMI Acknowledge 1st MC
INT0 Acknowledge 1st MC
BUS RELEASE mode
SLEEP mode
SYSTEM STOP mode
Note: nw = the number of Wait States; MC: Machine Cycle
E Clock Timing in Each Condition
1st Tw rise - T3 fall
Duration of E Clock Output High
T2 rise - T3 fall
1st Tw rise - T3 fall
1st Tw rise - T3 rise
T2 rise - T3 fall
Phi fall - Phi fall
(1.5 Phi + nw x Phi)
(0.5Phi + nw x Phi)
In
(1.5 Phi)
(0.50 + nw x Phi
(2 Phi or 1 Phi)
w
x Phi)
)