Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 133

IC 10MHZ Z180 CMOS ENH MPU 64DIP

Z8018010PSG

Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Datasheets

Specifications of Z8018010PSG

Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
118
ASCI Transmit Data Register Ch. 0 (TDR0: 06H)
UM005003-0703
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
ASCI Transmit Data Register Ch. 1 (TDR1: 07H)
Z8018x
Family MPU User Manual
7
7
When transmission is completed, the next byte (if available) is
automatically loaded from TDR into TSR and the next transmission
starts. If no data is available for transmission, TSR idles by outputting a
continuous High level. The TSR is not program-accessible.
ASCI Transmit Data Register 0, 1(TDR0,1:I/O Address = 06H, 07H)
Data written to the ASCI Transmit Data Register is transferred to the TSR
as soon as TSR is empty. Data can be written while TSR is shifting out the
previous byte of data. Thus, the ASCI transmitter is double buffered. Data
can be written into and read from the ASCI Transmit Data Register.
If data is read from the ASCI Transmit Data Register, the ASCI data
transmit operation is not affected by this read operation.
6
6
5
5
ASCI Transmit Channel 0
ASCI Transmit Channel 1
4
4
R/W
R/W
0
0
3
3
2
2
1
1
0
0

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