Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 123

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

108
UM005003-0703
Z8018x
Family MPU User Manual
DREQ0
TEND0
Phi
Phi
rising edge of the clock prior to T3 at which time the DMA operation
(re)starts. Figure 48 depicts the edge-sense DMA timing.
Figure 48.
During the transfers for channel 0, the TEND0 output goes Low
synchronous with the write cycle of the last (BCR0 =
(Reference Figure 49).
Figure 49.
The DREQ0 and TEND0 pins are programmably multiplexed with the
CKA0 and CKA1 ASCI clock input/outputs. However, when DMA
channel 0 is programmed for memory to/from I/O (and memory to/from
DMA
Write
Cycle
Tw
**
T1
T3
T1
DMA read cycle
CPU
Machine
Cycle
CPU Operation and DMA Operation DREQ0 is Programmed
for Edge-Sense
TEND0 Output Timing Diagram
T2
T2
**
T3
Last DMA cycle (BCR0 = 00H)
T3
T1
DMA
Read
Cycle
T2
T3
T1
T1
DMA write cycle
T2
T2
DMA
Write
Cycle
Tw
**
** DREQ0 is sampled at
T3
TW
T1
CPU
Machine
Cycle
T2
**
T3
T3
OOH
) DMA transfer