Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 43

IC 10MHZ Z180 CMOS ENH MPU 64DIP

Z8018010PSG

Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Datasheets

Specifications of Z8018010PSG

Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
28
UM005003-0703
Z8018x
Family MPU User Manual
Dynamic RAM refresh is not performed during Wait States (TW) and thus
system designs which use the automatic refresh function must consider
the affects of the occurrence and duration of wait states (TW). Figure 18
depicts WAIT timing.
Figure 18.
Programmable Wait State Insertion
In addition to the WAIT input, Wait States (TW) can also be inserted by
program using the Z8X180 on-chip Wait State generator (see Figure 19.
Wait State (TW) timing applies for both CPU execution and on-chip
DMAC cycles.
By programming the four significant bits of the DMA/Wait Control
Register (DCNTL) the number of Wait States, (TW) automatically
inserted in memory and I/O cycles, can be separately specified. Bits 4 and
5 specify the number of Wait States (TW) inserted for I/O access and bits
6 and 7 specify the number of Wait States (TW) inserted for memory
access. These bit pairs all 0–3 programmed Wait States for either I/O or
memory access.
WAIT
Phi
externally synchronizing WAIT input transitions with the rising
edge of the system clock.
WAIT Timing Diagram
T1
T2
TW
TW
T3
T1

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