Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 128

IC 10MHZ Z180 CMOS ENH MPU 64DIP

Z8018010PSG

Manufacturer Part Number
Z8018010PSG
Description
IC 10MHZ Z180 CMOS ENH MPU 64DIP
Manufacturer
Zilog
Datasheets

Specifications of Z8018010PSG

Processor Type
Z180
Features
8-Bit, Enhanced Z80 Megacell
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
64-DIP (0.750", 19.05mm)
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Minimum Operating Temperature
0 C
Core Size
8bit
Cpu Speed
10MHz
Digital Ic Case Style
DIP
No. Of Pins
64
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
8018010
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3889
Z8018010PSG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8018010PSG
Manufacturer:
Zilog
Quantity:
40
Z8018x
Family MPU User Manual
113
cycle is extended to 4 clocks by automatic insertion of one internal Ti
state.
DMAC Channel Priority
For simultaneous DREQ0 and DREQ1 requests, channel 0 has priority
over channel 1. When channel 0 is performing a memory to/from memory
transfer, channel 1 cannot operate until the channel 0 operation has
terminated. If channel 1 is operating, channel 0 cannot operate until
channel 1 releases control of the bus.
DMAC and BUSREQ, BUSACK
The BUSREQ and BUSACK inputs allow another bus master to take
control of the Z8X180 bus. BUSREQ and BUSACK take priority over the
on-chip DMAC and suspends DMAC operation. The DMAC releases the
bus to the external bus master at the breakpoint of the DMAC memory or
I/O access. Since a single byte DMAC transfer requires a read and a write
cycle, it is possible for the DMAC to be suspended after the DMAC read,
but before the DMAC write. Hence, when the external master releases the
Z8X180 bus (BUSREQ High), the on-chip DMAC correctly continues
the suspended DMA operation.
UM005003-0703

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