Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 54

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

STANDBY Mode EXit with External Interrupts
If the BREXT bit of the CPU Control Register (CCR) is cleared, asserting
the BUSREQ does not cause the Z8S180/Z8L180-class processors to exit
STANDBY mode.
If STANDBY mode is exited because of a reset or an external interrupt,
the Z8S180/Z8L180-class processors remains relinquished from the
system bus as long as BUSREQ is active.
STANDBY mode can be exited by asserting input NMI. The STANDBY
mode may also exit by asserting INT0. INT1 or INT2, depending on the
conditions specified in the following paragraphs.
INT0 wake-up requires assertion throughout duration of clock
stabilization time (2
If exit conditions are met, the internal counter provides time for the
crystal oscillator to stabilize, before the internal clocking and the system
clock output within the Z8S180/Z8L180-class processors resume.
•
•
If an interrupt source is disabled in the ITC, asserting the corresponding
interrupt input does not cause the Z8S180/Z8L180-class processors to
exit STANDBY mode. This condition is true regardless of the state of the
Global Interrupt Enable Flag IEF1.
Exit with Non-Maskable Interrupts
If NMI is asserted, the CPU begins a normal NMI interrupt
acknowledge sequence after clocking resumes.
Exit with External Maskable Interrupts
If an External Maskable Interrupt input is asserted, the CPU responds
according to the status of the Global Interrupt Enable Flag IEF1
(determined by the ITE1 bit) and the settings of the corresponding
interrupt enable bit in the Interrupt/Trap Control Register (ITC: I/O
Address =
34H
).
17
clocks).
Family MPU User Manual
UM005003-0703
Z8018x
39