Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 48

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

INT1, NMI
.
A0
Figure 20.
SLEEP Mode
SLEEP mode is entered by execution of the 2-byte SLP instruction.
SLEEP mode contains the following characteristics:
•
•
•
•
•
•
•
•
MREQ
HALT
–
A19
The internal CPU clock stops, reducing power consumption
The internal crystal oscillator does not stop
Internal and external interrupt inputs can be received
DRAM refresh cycles stop
I/O operations using on-chip peripherals continue
The internal DMAC stop
BUSREQ can be received and acknowledged
Address outputs go High and all other control signal outputs become
inactive High
Phi
RD
M1
HALT Op Code address
HALT Timing Diagram
T1
HALT Op Code
Fetch Cycle
T3
T1
HALT mode
HALT Op Code address + 1
T2
Family MPU User Manual
T3
T1
Interrupt
acknowledge cycle
UM005003-0703
Z8018x
T2
33