EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 902

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Glossary
1–390
Stratix III Device Handbook, Volume 2
Table 1–206. Glossary Table
Letter
S
SW (sampling
window)
Single-ended
Voltage
Referenced I/O
Standard
Subject
The period of time during which the data must be valid in order to capture it correctly.
The setup and hold times determine the ideal strobe position within the sampling
window (the following figure):
Timing Diagram
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC
input signal values. The AC values indicate the voltage levels at which the receiver
must meet its timing specifications. The DC values indicate the voltage levels at
which the final logic state of the receiver is unambiguously defined. Once the
receiver input has crossed the AC value, the receiver will change to the new logic
state.
The new logic state will then be maintained as long as the input stays beyond the AC
threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing (The following figure):
Single-Ended Voltage Referenced I/O Standard
0.5 x TCCS
V
V
OH
OL
RSKM
Sampling Window
Bit Time
(SW)
Definitions
V
REF
RSKM
0.5 x TCCS
V
V
IH(DC)
IL(DC)
Altera Corporation
November 2007
V
V
IH ( AC )
IL(AC )
V
CCIO
V
SS