EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 484

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Error Detection Block
15–10
Stratix III Device Handbook, Volume 1
Table 15–5
Syndrome Register
Error Message Register
JTAG Update Register
User Update Register
JTAG Shift Register
User Shift Register
Table 15–5. Error Detection Registers (Part 1 of 2)
Register
defines the registers shown in
This register contains the CRC signature of the
current frame through the error detection
verification cycle. The
derived from the contents of this register.
This 46-bit register contains information on the
error type, location of the error and the actual
syndrome. The types of errors and location
reported are single and double-adjacent bit errors.
The location bits for other types of errors are not
identified by the Error Message Register. The
content of the register can be shifted out through
the JTAG
to the core through the core interface.
This register is automatically updated with the
contents of the Error Message Register one cycle
after the 46-bit register content is validated. It
includes a clock enable which should be asserted
prior to being sampled into the JTAG Shift Register.
This requirement ensures that the JTAG Update
Register is not being written into by the contents of
the Error Message Register at exactly the same
time that the JTAG Shift Register is reading its
contents.
This register is automatically updated with the
contents of the Error Message Register, one cycle
after the 46-bit register content is validated. It
includes a clock enable which should be asserted
prior to being sampled into the User Shift Register.
This requirement ensures that the User Update
Register is not being written into by the contents of
the Error Message Register at exactly the same
time that the User Shift Register is reading its
contents.
This register is accessible by the JTAG interface
and allows the contents of the JTAG Update
Register to be sampled and read out by JTAG
instruction
This register is accessible by the core logic and
allows the contents of the User Update Register to
be sampled and read by user logic.
SHIFT_EDERROR_REG
SHIFT_EDERROR_REG
Figure
Description
CRC_ERROR
15–2.
Altera Corporation
.
instruction or
signal is
October 2007