EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 538

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Switching Characteristics
1–26
Stratix III Device Handbook, Volume 2
Table 1–31
devices.
Notes to
(1)
(2)
(3)
Table 1–31. DQS Phase Offset Delay per Stage
Preliminary
Speed Grade
The delay settings are linear.
The DQS phase shift is the sum of the DLL delay settings and the user selected
phase offset settings. The valid settings for phase offset are -64 to +63 for
frequency mode 0 and -32 to +31 for frequency modes 1, 2, and 3. You should
continuously monitor the DLL delay settings to determine how many phase
offset settings are available for your system.
The typical value equals the average of the minimum and maximum values.
-2
-3
-4
Table
describes the DQS Phase Offset Delay per stage for Stratix III
1–31:
Min
9
9
9
Max
14
14
14
Notes
(1), (2),
Altera Corporation
November 2007
(3)
Unit
ps
ps
ps
-