EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 373

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
INIT_DONE pin is released and pulled high. The MAX II device must be
able to detect this low-to-high transition, which signals the device has
entered user mode. When initialization is complete, the device enters user
mode. In user-mode, the user I/O pins no longer have weak pull-up
resistors and function as assigned in your design.
To ensure DCLK and DATA[7..0] are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
whichever is convenient on your board. The DATA[7..0] pins are
available as user I/O pins after configuration. When you select the FPP
scheme as a default in the Quartus II software, these I/O pins are
tri-stated in user mode. To change this default option in the Quartus II
software, select the Dual-Purpose Pins tab of the Device and Pin
Options dialog box.
The configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
1
By stopping DCLK, the configuration circuit allows enough clock cycles to
process the last byte of latched configuration data. When the clock
restarts, the MAX II device must provide data on the DATA[7..0] pins
prior to sending the first DCLK rising edge.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the MAX II device that there is an error. If the Auto-restart
configuration after error option (available in the Quartus II software
from the General tab of the Device and Pin Options dialog box) is turned
on, the device releases nSTATUS after a reset time-out period (maximum
of 100 ms). After nSTATUS is released and pulled high by a pull-up
resistor, the MAX II device can try to reconfigure the target device
without needing to pulse nCONFIG low. If this option is turned off, the
MAX II device must generate a low-to-high transition (with a low pulse
of at least 2 ms) on nCONFIG to restart the configuration process.
If you are using the Stratix III decompression and/or design
security feature and need to stop DCLK, it can only be stopped
three clock cycles after the last data byte was latched into the
Stratix III device.
Stratix III Device Handbook, Volume 1
Configuring Stratix III Devices
11–13