EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 313

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
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The output path is designed to route combinatorial or registered SDR
outputs and full-rate or half-rate DDR outputs from the FPGA core.
Half-rate data is converted to full-rate using the HDR block, clocked by
the half-rate clock from the PLL. The resynchronization registers are also
clocked by the same 0° system clock, except in the DDR3 SDRAM
interface. In DDR3 SDRAM interfaces, the leveling registers are clocked
by the write-leveling clock.
For more information on the write leveling delay chain, refer to the
“Leveling Circuitry”
The output-enable path has structure similar to the output path. You can
have a combinatorial or registered output in SDR applications and you
can use half-rate or full-rate operation in DDR applications. You also have
the resynchronization registers like the output path registers structure,
ensuring that the output enable path goes through the same delay and
latency as the output path.
IOE Features
This section briefly describes how OCT, programmable delay chains,
programmable output delay, slew rate adjustment, and programmable
drive strength can be useful in memory interfaces.
For more information about any of the features listed below, refer to the
Stratix III Device I/O Features
Handbook.
OCT
Stratix III devices feature dynamic calibrated OCT, in which the series
termination (OCT R
when receiving signals, while the parallel termination (OCT R
off when driving signals and turned on when receiving signals. This
feature complements the DDR3/DDR2 SDRAM on-die termination
(ODT), whereby the memory termination is turned off when the memory
is sending data and turned on when receiving data. You can use OCT for
other memory interfaces to improve signal integrity.
1
To use the dynamic calibrated OCT, you must use the R
to calibrate the OCT calibration block. One OCT calibration block can be
used to calibrate one type of termination with the same V
You cannot use the programmable drive strength and
programmable slew rate features when using OCT R
S
) is turned on when driving signals and turned off
section on
External Memory Interfaces in Stratix III Devices
chapter in volume 1 of the Stratix III Device
page
Stratix III Device Handbook, Volume 1
8–36.
UP
CCIO
and R
T
S
on the
) is turned
.
DN
pins
8–43