EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 151

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Introduction
Clock Networks
in Stratix III
Devices
Altera Corporation
November 2007
SIII51006-1.3
Stratix
PLLs with advanced features. The large number of clocking resources, in
combination with the clock synthesis precision provided by the PLLs,
provides a complete clock management solution. Stratix III devices
provide dedicated global clock networks (GCLKs), regional clock
networks (RCLKs), and periphery clock networks (PCLKs). These clocks
are organized into a hierarchical clock structure that provides up to 220
unique clock domains (16 GCLK + 88 RCLK + 116 PCLK) within the
Stratix III device and allows up to 67 unique GCLK, RCLK, and PCLK
clock sources (16 GCLK + 22 RCLK + 29 PCLK) per device quadrant. The
Altera
networks not used in the design, thereby reducing the overall power
consumption of the device.
Stratix III devices deliver abundant PLL resources with up to 12 PLLs per
device and up to 10 outputs per PLL. You can independently program
every output, creating a unique, customizable clock frequency with no
fixed relation to any other input or output clock. Inherent jitter filtration
and fine granularity control over multiply, divide ratios, and dynamic
phase shift reconfiguration provide the high performance precision
required in today's high-speed applications. Stratix III device PLLs are
feature rich, supporting advanced capabilities such as clock switchover,
dynamic phase shifting, PLL reconfiguration, and reconfigurable
bandwidth. Stratix III PLLs also support external feedback mode,
spread-spectrum tracking, and post-scale counter cascading features.
The Quartus II software enables the PLLs and their features without
requiring any external devices. The following sections describe the
Stratix III clock networks and PLLs in detail.
The GCLKs, RCLKs, and PCLKs available in Stratix III devices are
organized into hierarchical clock structures that provide up to 220 unique
clock domains (16 GCLK + 88 RCLK + 116 PCLK) within the Stratix III
device and allows up to 67 unique GCLK, RCLK, and PCLK clock sources
(16 GCLK + 22 RCLK + 29 PCLK) per device quadrant.
the clock resources available in Stratix III devices.
®
®
Quartus
III devices provide a hierarchical clock structure and multiple
®
6. Clock Networks and PLLs
II software compiler automatically turns off clock
in Stratix III Devices
Table 6–1
shows
6–1