EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 10

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Contents
Section IV. Design Security & Single Event Upset (SEU) Mitigation
Chapter 14. Design Security in Stratix III Devices
Chapter 15. SEU Mitigation in Stratix III Devices
Section V. Power and Thermal Management
Chapter 16. Programmable Power and Temperature Sensing Diode in Stratix III Devices
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Introduction .......................................................................................................................................... 14–1
Stratix III Security Protection ............................................................................................................. 14–2
AES Decryption Block ......................................................................................................................... 14–3
Flexible Security Key Storage ............................................................................................................ 14–3
Stratix III Design Security Solution ................................................................................................... 14–4
Security Modes Available ................................................................................................................... 14–5
Supported Configuration Schemes ................................................................................................... 14–6
Conclusion ............................................................................................................................................ 14–9
Referenced Documents ....................................................................................................................... 14–9
Document Revision History ............................................................................................................... 14–9
Introduction .......................................................................................................................................... 15–1
Configuration Error Detection ........................................................................................................... 15–2
User Mode Error Detection ................................................................................................................ 15–2
Error Detection Pin Description ........................................................................................................ 15–7
Error Detection Block .......................................................................................................................... 15–8
Error Detection Timing ..................................................................................................................... 15–11
Recovering From CRC Errors .......................................................................................................... 15–14
Conclusion .......................................................................................................................................... 15–14
Referenced Documents ..................................................................................................................... 15–14
Document Revision History ............................................................................................................. 15–14
Introduction .......................................................................................................................................... 16–1
Stratix III Power Technology ............................................................................................................. 16–2
Stratix III External Power Supply Requirements ............................................................................ 16–5
Security Against Copying ............................................................................................................. 14–2
Security Against Reverse Engineering ........................................................................................ 14–2
Security Against Tampering ......................................................................................................... 14–2
Automated Single Event Upset Detection .................................................................................. 15–6
Critical Error Detection ................................................................................................................. 15–6
CRC_ERROR Pin ............................................................................................................................ 15–7
CRITICAL ERROR Pin .................................................................................................................. 15–8
Error Detection Registers .............................................................................................................. 15–9
Software Support .......................................................................................................................... 15–12
Selectable Core Voltage ................................................................................................................. 16–2
Programmable Power Technology .............................................................................................. 16–3
Relationship Between Selectable Core Voltage and Programmable Power Technology .... 16–4
Stratix III Device Handbook, Volume 2
Altera Corporation