EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 198

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

PLLs in Stratix III Devices
Figure 6–34. Open- and Closed-Loop Response Bode Plots
6–48
Stratix III Device Handbook, Volume 1
Open-Loop Reponse Bode Plot
Closed-Loop Reponse Bode Plot
Gain
Gain
0 dB
A high-bandwidth PLL provides a fast lock time and tracks jitter on the
reference clock source, passing it through to the PLL output. A
low-bandwidth PLL filters out reference clock jitter but increases lock
time. Stratix III PLLs allow you to control the bandwidth over a finite
range to customize the PLL characteristics for a particular application.
The programmable bandwidth feature in Stratix III PLLs benefits
applications requiring clock switchover.
A high-bandwidth PLL can benefit a system that needs to accept a
spread-spectrum clock signal. Stratix III PLLs can track a
spread-spectrum clock by using a high-bandwidth setting. Using a
low-bandwidth in this case could cause the PLL to filter out the jitter on
the input clock.
Frequency
Frequency
Increasing the PLL's
bandwidth in effect pushes
the open loop response out.
Altera Corporation
November 2007