EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 302

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III External Memory Interface Features
Figure 8–13. Stratix III DQS Logic Block
Note to
(1)
(2)
8–32
Stratix III Device Handbook, Volume 1
DQS phase shift
settings from the
settings from
Phase offset
shift circuitry
DQS phase-
DQS delay
The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin.
Refer to
The dqsenable signal can also come from the Stratix III FPGA fabric.
circuitry
Figure
Tables 8–8
6
6
8–13:
CQn Pin
DQS or
6
Bypass
D
through
Input Reference
Q
6
Clock (1)
When using the static phase offset, you can specify the phase offset
amount in the ALTMEMPHY megafunction as a positive number for
addition or a negative number for subtraction. You can also have a
dynamic phase offset that is always added to, subtracted from, or both
added to and subtracted from the DLL phase shift. When you always add
or subtract, you can dynamically input the phase offset amount into the
dll_offset[5..0] port. When you want to both add and subtract
dynamically, you control the addnsub signal in addition to the
dll_offset[5..0] signals.
DQS Logic Block
Each DQS and CQn pin is connected to a separate DQS logic block, which
consists of the DQS delay chains, the update enable circuitry, and the
DQS postamble circuitry (see
8–11
6
for the exact PLL and input clock pin.
DQS Delay Chain
D
Q
6
6
Circuitry
Update
Enable
Figure
Resynchronization
Postamble
Postamble
8–13).
Enable
Clock
Clock
DQS Enable
B
A
D
DQS'
Q
gated_dqs control
Altera Corporation
DQS bus
D
D
November 2007
reset
dqsenable
Q
Q
DFF
Q
PRN
CLR
D
V
CC