EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 111

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 5–6. Half-DSP Block Architecture
Altera Corporation
October 2007
datab_2[ ]
datab_3[ ]
datab_1[ ]
dataa_2[ ]
dataa_3[ ]
dataa_0[ ]
datab_0[ ]
dataa_1[ ]
scanina[ ]
chainin[ ]
loopback
clock[3..0]
ena[3..0]
alcr[3..0]
Half-DSP Block
Input Registers
All of the DSP block registers are triggered by the positive edge of the
clock signal and are cleared upon power up. Each multiplier operand can
feed an input register or directly to the multiplier, bypassing the input
registers. (This is configured at compile time.) The following DSP block
signals control the input registers within the DSP block:
■
■
■
clock[3..0]
ena[3..0]
aclr[3..0]
chainout_saturate
chainout_round
zero_loopback
zero_chainout
accum_sload
output_saturate
output_round
shift_right
rotate
signa
signb
Stratix III Device Handbook, Volume 1
DSP Blocks in Stratix III Devices
overflow
chainout_sat_overflow
result[ ]
5–11