EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 393

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
.hex, or .ttf format, you must send the least significant bit (LSB) of each
data byte first. For example, if the RBF contains the byte sequence 02 1B
EE 01 FA, the serial bitstream you should transmit to the device is
0100-0000 1101-1000 0111-0111 1000-0000 0101-1111.
The Stratix III device receives configuration data on the DATA0 pin and
the clock is received on the DCLK pin. Data is latched into the device on
the rising edge of DCLK. Data is continuously clocked into the target
device until CONF_DONE goes high. After the device has received all
configuration data successfully, it releases the open-drain CONF_DONE
pin, which is pulled high by an external 10-kΩ pull-up resistor. A
low-to-high transition on CONF_DONE indicates configuration is complete
and initialization of the device can begin. The CONF_DONE pin must have
an external 10-kΩ pull-up resistor in order for the device to initialize.
In Stratix III devices, the initialization clock source is either the internal
oscillator (typically 10 MHz) or the optional CLKUSR pin. By default, the
internal oscillator is the clock source for initialization. If you use the
internal oscillator, the Stratix III device provides itself with enough clock
cycles for proper initialization. Therefore, if the internal oscillator is the
initialization clock source, sending the entire configuration file to the
device is sufficient to configure and initialize the device. Driving DCLK to
the device after configuration is complete does not affect device
operation.
You also have the flexibility to synchronize initialization of multiple
devices or to delay initialization with the CLKUSR option. You can turn on
the Enable user-supplied start-up clock (CLKUSR) option in the
Quartus II software from the General tab of the Device and Pin Options
dialog box. If you supply a clock on CLKUSR, it will not affect the
configuration process. After all configuration data has been accepted and
CONF_DONE goes high, CLKUSR will be enabled after the time specified as
t
clock cycles to initialize properly and enter user mode. Stratix III devices
support a CLKUSR f
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device and Pin Options dialog box.
If you use the INIT_DONE pin, it will be high due to an external 10-kΩ
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. The MAX II device
must be able to detect this low-to-high transition which signals the device
CD2CU
. After this time period elapses, Stratix III devices require 4,436
MAX
of 100 MHz.
Stratix III Device Handbook, Volume 1
Configuring Stratix III Devices
11–33