EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 197

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 6–33. VCO Switchover Operating Frequency
Altera Corporation
November 2007
ΔF vco
Primary Clock Stops Running
■
■
Programmable Bandwidth
Stratix III PLLs provide advanced control of the PLL bandwidth using the
PLL loop's programmable characteristics, including loop filter and charge
pump.
Background
PLL bandwidth is the measure of the PLL's ability to track the input clock
and its associated jitter. The closed-loop gain 3-dB frequency in the PLL
determines the PLL bandwidth. The bandwidth is approximately the
unity gain point for open loop PLL response. As
points correspond to approximately the same frequency. Stratix III PLLs
provide three bandwidth settings—low, medium (default), and high.
Figure 6–33
when the current clock is lost and then increases as the VCO locks on
to the backup clock.
Disable the system during clock switchover if it is not tolerant of
frequency variations during the PLL resynchronization period. You
can use the clkbad[0] and clkbad[1] status signals to turn off the
PFD (PFDENA = 0) so the VCO maintains its most recent frequency.
You can also use the state machine to switch over to the secondary
clock. When the PFD is re-enabled, output clock-enable signals
(clkena) can disable clock outputs during the switchover and
resynchronization period. Once the lock indication is stable, the
system can re-enable the output clock(s).
shows how the VCO frequency gradually decreases
Switchover Occurs
Clock Networks and PLLs in Stratix III Devices
Stratix III Device Handbook, Volume 1
Figure 6–34
VCO Tracks Secondary Clock
shows, these
6–47