EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 481

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Error Detection
Pin Description
Altera Corporation
October 2007
Figure 15–1. Critical Error Detection Implementation Block Diagram
1
Depending on the type of error detection feature you choose, you will
need to use different error detection pins to monitor the data during user
mode.
CRC_ERROR Pin
Table 15–3
CRC_ERROR
Table 15–3. CRC_ERROR Pin Description
Pin Name
This reference design will be supported in future versions of the
Quartus II software.
CRC Checker
Sensitivity
Processor
describes the CRC_ERROR pin.
(Hard Logic)
(Soft IP)
I/O, output
Pin Type
Stratix III FPGA
Active high signal that indicates that the error
detection circuit has detected errors in the
configuration CRAM bits. This pin is optional and
is used when the error detection CRC circuit is
enabled. When the error detection CRC circuit is
disabled, it is a user I/O pin. The CRC error output,
when using the WYSIWYG function, is a
dedicated path to the
CRC_ERROR
Memory Access
(User Designed)
Logic
Stratix III Device Handbook, Volume 1
SEU Mitigation in Stratix III Devices
pin supports open-drain.
Description
CRC_ERROR
Serial / Parallel
Flash
CRITICAL ERROR
CRC_ERROR
pin. The
15–7