EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 81

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 4–4. Stratix III Address Clock Enable during Write Cycle Waveform
Altera Corporation
November 2007
latched address
(inside memory)
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
addressstall
wraddress
inclock
wren
data
an
XX
Figure 4–4
Mixed Width Support
M9K and M144K memory blocks support mixed data widths inherently.
MLABs can support mixed data widths through emulation via the
Quartus II software. When using simple dual-port, true dual-port, or
FIFO modes, mixed width support allows you to read and write different
data widths to a memory block. See
details on the different widths supported per memory mode.
Asynchronous Clear
Stratix III TriMatrix memory blocks support asynchronous clears on the
output latches and output registers. Therefore, if your RAM is not using
the output registers, you can still clear the RAM outputs via the output
latch asynchronous clear. A functional waveform showing this
functionality is shown in
a0
00
XX
a0
a1
01
shows the address clock enable waveform during write cycle.
XX
01
TriMatrix Embedded Memory Blocks in Stratix III Devices
02
a2
XX
Figure
XX
XX
a1
02
a3
03
4–5.
00
“Memory Modes” on page 4–9
Stratix III Device Handbook, Volume 1
04
a4
a4
03
a5
05
04
a5
05
a6
06
for
4–7