EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 288

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Memory Interfaces Pin Support
8–18
Stratix III Device Handbook, Volume 1
DM and QVLD pins) and a pair of DQS and DQSn/CQn pins. Similarly,
in ×16/×18 mode, the I/O bank combines four adjacent ×4 DQS/DQ
groups to create a group with a maximum of 19 DQ pins (including parity
or DM and QVLD pins) and a pair of DQS and DQSn/CQn pins. In
×32/×36 mode, the I/O bank combines eight adjacent ×4 DQS DQ groups
together to create a group with a maximum of 37 DQ pins (including
parity or DM and QVLD pins) and a pair of DQS and DQSn/CQn pins.
Stratix III modular I/O banks allow easy formation of the DQS/DQ
groups. If all the pins in the I/O banks are user I/O pins and are not used
for programming, R
output pins, you can divide the number of I/O pins in the bank by 6 to
get the maximum possible number of ×4 groups. You can then divide that
number by 2, 4, or 8 to get the maximum possible number of ×8/×9,
×16/×18, or ×32/×36, respectively (see
pins in the I/O bank may be used for other functions.
Optional Parity, DM, BWSn, ECC and QVLD Pins
You can use any of the DQ pins from the same DQS/DQ group for data
as parity pins in Stratix III devices. The Stratix III device family supports
parity in the ×8/×9, ×16/×18, and ×32/×36 modes. There is one parity bit
available per eight bits of data pins. Use any of the DQ (or D) pins in the
same DQS/DQ group as data for parity as they are treated, configured,
and generated like a DQ pin.
The data mask (DM) pins are only required when writing to DDR3,
DDR2, DDR SDRAM, and RLDRAM II devices. QDRII+ and QDRII
SRAM devices use the BWSn signal to select which byte to write into the
memory. A low signal on the DM or BWSn signals indicates that the write
Note to
(1)
24 pins
32 pins
40 pins
48 pins
Modular I/O
Table 8–6. DQ/DQS Group in Stratix III Modular I/O Banks
Bank Size
Some of the ×4 groups may use RUP/RDN pins. You cannot use these groups if
you use the Stratix III calibrated OCT feature.
Table
8–6:
×4 Groups
Number of
Maximum
Possible
UP
4
5
6
8
/R
(1)
DN
used for OCT calibration, or PLL clock
×8/×9 Groups
Number of
Maximum
Possible
2
2
3
4
Table
8–6). However, some of the
Number of
Maximum
Possible
×16/×18
Groups
1
1
1
2
Altera Corporation
November 2007
Number of
Maximum
Possible
×32/×36
Groups
0
0
0
1