EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 171

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 6–15. clkena Signals
Note to
(1)
Altera Corporation
November 2007
gate with R2 not bypassed
gate with R2 bypassed
You can use the clkena signals to enable or disable the global and regional networks or the PLL_<#>_CLKOUT
pins.
Figure
output of AND
output of AND
select mux
output of
clkena
clock
6–15:
The PLL can remain locked independent of the clkena signals since the
loop-related counters are not affected. This feature is useful for
applications that require a low power or sleep mode. The clkena signal
can also disable clock outputs if the system is not tolerant of frequency
over-shoot during resynchronization.
Clock Networks and PLLs in Stratix III Devices
Stratix III Device Handbook, Volume 1
6–21