EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 193

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
generates a signal (clksw) that controls the multiplexer select input as
shown in
for the PLL. When using the automatic switchover mode, you can switch
back and forth between inclk0 and inclk1 clocks any number of times,
when one of the two clocks fails and the other clock is available.
When using the automatic clock switchover mode, the following
requirements need to be satisfied:
■
■
If the current clock input stops toggling while the other clock is also not
toggling, switchover will not be initiated and the clkbad[0:1] signals
will not be valid. Also, if both clock inputs are not the same frequency, but
their period difference is within 100%, the clock sense block will detect
when a clock stops toggling, but the PLL may lose lock after the
switchover is completed and need time to relock.
1
When using automatic switchover mode, the clkbad[0] and
clkbad[1] signals indicate the status of the two clock inputs. When they
are asserted, the clock sense block has detected that the corresponding
clock input has stopped toggling. These two signals are not valid if the
frequency difference between inclk0 and inclk1 is greater than 20%.
The activeclock signal indicates which of the two clock inputs
(inclk0 or inclk1) is being selected as the reference clock to the PLL.
When the frequency difference between the two clock inputs is more than
20%, the activeclock signal is the only valid status signal.
Figure 6–30
using the automatic switchover mode. In this example, the inclk0 signal
is stuck low. After the inclk0 signal is stuck at low for approximately
two clock cycles, the clock sense circuitry drives the clkbad[0] signal
high. Also, because the reference clock signal is not toggling, the
switchover state machine controls the multiplexer through the clksw
signal to switch to the backup clock, inclk1.
Both clock inputs need to be running.
The period of the two clock inputs can differ by no more than 100%
(2×).
Altera recommends resetting the PLL using the areset signal
to maintain the phase relationships between the PLL input and
output clocks when using clock switchover.
Figure
shows an example waveform of the switchover feature when
6–29. In this case, inclk1 becomes the reference clock
Clock Networks and PLLs in Stratix III Devices
Stratix III Device Handbook, Volume 1
6–43