EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 6

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Contents
Section II. I/O Interfaces
Chapter 7. Stratix III Device I/O Features
vi
Conclusion ............................................................................................................................................ 6–64
Referenced Documents ....................................................................................................................... 6–64
Document Revision History ............................................................................................................... 6–65
Introduction ............................................................................................................................................ 7–1
Stratix III I/O Standards Support ....................................................................................................... 7–1
Stratix III I/O Banks .............................................................................................................................. 7–5
Stratix III I/O Structure ...................................................................................................................... 7–14
OCT Support ........................................................................................................................................ 7–23
OCT Calibration ................................................................................................................................... 7–30
Termination Schemes for I/O Standards ......................................................................................... 7–37
Stratix III PLL Hardware Overview ............................................................................................ 6–24
Stratix III PLL Software Overview ............................................................................................... 6–28
Clock Feedback Modes .................................................................................................................. 6–32
Clock Multiplication and Division .............................................................................................. 6–38
Post-Scale Counter Cascading ...................................................................................................... 6–39
Programmable Duty Cycle ........................................................................................................... 6–40
PLL Control Signals ....................................................................................................................... 6–40
Clock Switchover ............................................................................................................................ 6–41
Programmable Bandwidth ............................................................................................................ 6–47
Phase-Shift Implementation ......................................................................................................... 6–50
PLL Reconfiguration ...................................................................................................................... 6–52
Spread-Spectrum Tracking ........................................................................................................... 6–64
PLL Specifications .......................................................................................................................... 6–64
I/O Standards and Voltage Levels ................................................................................................ 7–3
Modular I/O Banks .......................................................................................................................... 7–8
3.3-V I/O Interface ......................................................................................................................... 7–15
External Memory Interfaces .......................................................................................................... 7–17
High-Speed Differential I/O with DPA Support ...................................................................... 7–17
Programmable Current Strength ................................................................................................. 7–18
Programmable Slew Rate Control ............................................................................................... 7–19
Programmable Delay ..................................................................................................................... 7–20
Open-Drain Output ........................................................................................................................ 7–20
Bus Hold .......................................................................................................................................... 7–21
Programmable Pull-Up Resistor .................................................................................................. 7–21
Programmable Pre-Emphasis ....................................................................................................... 7–22
Programmable Differential Output Voltage .............................................................................. 7–22
MultiVolt I/O Interface ................................................................................................................. 7–22
LVDS Input On-Chip Termination (R
OCT Calibration Block Location .................................................................................................. 7–30
OCT Calibration Block Modes of Operation .............................................................................. 7–33
Single-Ended I/O Standards Termination ................................................................................. 7–37
D
) ..................................................................................... 7–29
Stratix III Device Handbook, Volume 2
Altera Corporation